1. Field of the Invention
This invention relates to the top metallization layer of a semiconductor memory device and more particularly to planarization of a passivation layer thereover.
2. Description of Related Art
In the backend process of manufacture of Enhanced Embedded DRAM (EDRAM) devices, we have found the passivation damage at a particular position. After gradually tracing the problem, the SOG gap-filling of passivation layer is the main issue and it causes the worst photoresist profile, therefore, the passivation damage is induced during etching of the passivation layer. We have concluded that the passivation damage results from a pocket or void which causes poor gap-filling above the SOG in the pocket regions. After passivation with a photoresist coating we have found by scanning with a alpha-stepper that the photoresist profile is not as flat and smooth as we anticipated. The poor gap filling is due to the density of metal lines which are formed in an array. The use of a thicker SOG layer did not help.
We have found that passivation damage is not avoidable for mask-sets for 0.35 EDRAM devices, (0.6 .mu.m/0.6 .mu.m) by using a current passivation scheme which is as follows:
Form M4-Fourth level Metallization PA1 Form 15,000 .ANG. SiON (PE SiON) PA1 Deposit 3,000 .ANG. SOG (Spin-On-Glass) PA1 Form 10,000 .ANG. SiN (Silicon Nitride)
Using such a process, the SOG layer is absorbed completely by the improper layout pattern (-4000 .mu.m comb-meander) at the edge of a die. This permits or causes the photoresist to flow into the gap in a succeeding photoresist processing step which involves a soft bake. Thus there is damage during the passivation etch due to poor SOG planarization.
U.S. Pat. No. 4,778,739 of Protschka for "Photoresist Process for Reactive Ion Etching of Metal Patterns for Semiconductor Devices" shows a photoresist rework process for metal lines.
U.S. Pat. No. 5,665,657 of Lee for "Spin-On-Glass Partial Etchback Planarization Process" shows a method for forming a planarization SOG layer which eliminates voids in SOG layers in between closely spaced conductive lines, employing an etch back process.
U.S. Pat. No. 5,567,660 of Chen et al. for "Spin-On-Glass Planarization by a New Stagnant Coating Method" shows a gap fill method to fill gaps between metal lines which method differs from the present invention.